Simulation and verification of various logic gates. - Computer Programming

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Friday, October 7, 2011

Simulation and verification of various logic gates.

OR GATE


AIM:


Simulation and verification of various logic gates.


PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(a,b:in bit;y:out bit);
end or2;
architecture or2 of or2 is
begin
y<=a or b;
end or2;

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