Design and verify full adder by using behavioural model with if,elsif& then statements. - Code

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Friday, October 7, 2011

Design and verify full adder by using behavioural model with if,elsif& then statements.

FULL ADDER


AIM:


Design and verify full adder by using behavioural model with if,elsif& then statements.


PROGRAM:


library ieee;
use ieee.std_logic_1164.all;
entity f ulladder is
port(a:in std_logic_vector(2 downto 0);
s,ca:out std_logic);
end fulladder;
architecture fulladder of f ulladder is
begin
process(a)
begin
if a="000" then s<='0';ca<='0';
elsif a="001" then s<='1';ca<='0';
elsif a="010" then s<='1';ca<='0';
elsif a="011" then s<='0';ca<='1';
elsif a="100" then s<='1';ca<='0';
elsif a="101" then s<='0';ca<='1';
elsif a="110" then s<='0';ca<='1';
else s<='1';ca<='1';
end if;
end process;
end fulladder;
SIMULATION OUTPUT:






RESULT: Full adder is simulated and verified

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