Design and verify full adder by using dataflow style . - Code

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Friday, October 7, 2011

Design and verify full adder by using dataflow style .

FULL ADDER
(DATAFLOW STYLE)


AIM:


Design and verify full adder by using dataflow style .


PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity f a1 is
port(a,b,c:in bit;s,cout:out bit);
end fa1;
architecture fa1 of fa1 is
begin
s<=a xor b xor c;
cout<=(a and b)or(a and c)or (b and c);
end fa1;


SIMULATION OUTPUT:




RESULT: Full adder is simulated and verified

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