**PARITY GENERATOR & CHECKER**

**AIM:**

**To design and verify the truth table of a three bit Odd Parity generator and checker.**

**APPARATUS REQUIRED:**

S.No | Name of the Apparatus | Range | Quantity |

1. | Digital IC trainer kit | 1 | |

2. | EX-OR gate | IC 7486 | |

3. | NOT gate | IC 7404 | |

4. | Connecting wires | As required |

**THEORY:**

**A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker.**

**In even parity the added parity bit will make the total number of 1’s an even amount and in odd parity the added parity bit will make the total number of 1’s an odd amount.**

**In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission.**

**Since the information was transmitted with odd parity the four bits received must have an odd number of 1’s. An error occurs during the transmission if the four bits received have an even number of 1’s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1’s.**

__ODD PARITY GENERATOR__**TRUTH TABLE:**

S.No | INPUT ( Three bit message) | OUTPUT( Odd Parity bit) | ||

A | B | C | P | |

1. | 0 | 0 | 0 | 1 |

2. | 0 | 0 | 1 | 0 |

3. | 0 | 1 | 0 | 0 |

4. | 0 | 1 | 1 | 1 |

5. | 1 | 0 | 0 | 0 |

6. | 1 | 0 | 1 | 1 |

7. | 1 | 1 | 0 | 1 |

8. | 1 | 1 | 1 | 0 |

**From the truth table the expression for the output parity bit is,**

**P( A, B, C) = Σ (0, 3, 5, 6)**

**Also written as,**

**P = A’B’C’ + A’BC + AB’C + ABC’ = (A**

**B**

**C) ‘**

**CIRCUIT DIAGRAM:**

__ODD PARITY GENERATOR__

__ODD PARITY CHECKER__**TRUTH TABLE:**

S.No | INPUT ( four bit messageReceived ) | OUTPUT(Parity error check) | |||

A | B | C | P | X | |

1. | 0 | 0 | 0 | 0 | 1 |

2. | 0 | 0 | 0 | 1 | 0 |

3. | 0 | 0 | 1 | 0 | 0 |

4. | 0 | 0 | 1 | 1 | 1 |

5. | 0 | 1 | 0 | 0 | 0 |

6. | 0 | 1 | 0 | 1 | 1 |

7. | 0 | 1 | 1 | 0 | 1 |

8. | 0 | 1 | 1 | 1 | 0 |

9. | 1 | 0 | 0 | 0 | 0 |

10. | 1 | 0 | 0 | 1 | 1 |

11. | 1 | 0 | 1 | 0 | 1 |

12. | 1 | 0 | 1 | 1 | 0 |

13. | 1 | 1 | 0 | 0 | 1 |

14. | 1 | 1 | 0 | 1 | 0 |

15. | 1 | 1 | 1 | 0 | 0 |

16. | 1 | 1 | 1 | 1 | 1 |

**From the truth table the expression for the output parity checker bit is,**

**X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15)**

**The above expression is reduced as,**

**X = (A**

**B**

**C**

**P) ‘**

**CIRCUIT DIAGRAM:**

__ODD PARITY CHECKER__

**PROCEDURE:**

**Connections are given as per the circuit diagrams.****For all the ICs 7**^{th }pin is grounded and 14^{th}pin is given +5 V supply.**Apply the inputs and verify the truth table for the Parity generator and checker.**

**RESULT:**

**The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified.**

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